1. Technical Field
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements associated with a multipurpose graded silicon oxynitride cap layer in non-volatile memory semiconductor devices.
2. Background Art
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of devices and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array is reduced by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell 8 is depicted in FIG. 1A, viewed in a cross-section through the bit line. Memory cell 8 includes a doped substrate 12 having a top surface 11, and a source 13a and a drain 13b formed by selectively doping regions of substrate 12. A tunnel oxide 15 separates a floating gate 16 from substrate 12. An interpoly dielectric 24 separates floating gate 16 from a control gate 26. Floating gate 16 and control gate 26 are each electrically conductive and typically formed of polysilicon.
On top of control gate 26 is a silicide layer 28, which acts to increase the electrical conductivity of control gate 26. Silicide layer 28 is typically a tungsten silicide (e.g., WSi.sub.2), that is formed on top of control gate 26 prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell 8 can be programmed, for example, by applying an appropriate programming voltage to control gate 26. Similarly, memory cell 8 can be erased, for example, by applying an appropriate erasure voltage to source 13a. When programmed, floating gate 16 will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate 16 can be programmed to a binary 1 by applying a programming voltage to control gate 26, which causes an electrical charge to build up on floating gate 16. If floating gate 16 does not contain a threshold level of electrical charge, then floating gate 16 represents a binary 0. During erasure, the charge is removed from floating gate 16 by way of the erasure voltage applied to source 13a.
FIG. 1B depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in FIG. 1A). In FIG. 1B, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate 12. For example, FIG. 1B shows a portion of a floating gate 16a associated with a first memory cell, a floating gate 16b associated with a second memory cell, and a floating gate 16c associated with a third memory cell. Floating gate 16a is physically separated and electrically isolated from floating gate 16b by a field oxide (FOX) 14a. Floating gate 16b is separated from floating gate 16c by a field oxide 14b. Floating gates 16a, 16b, and 16c are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate 12, tunnel oxide 15, and field oxides 14a and 14b. Interpoly dielectric layer 24 has been conformally deposited over the exposed portions of floating gates 16a, 16b, and 16c and field oxides 14a and 14b. Interpoly dielectric layer 24 isolates floating gates 16a, 16b and 16c from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate 26. Interpoly dielectric layer 24 typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the basic features depicted in the memory cells of FIGS. 1A and 1B, placed a burden on the fabrication process to deposit and subsequently pattern a layer stack to form a floating gate/control gate structure, without creating deleterious effects within the resulting memory cells.
In particular, the reduction in critical dimensions reduces the yield of semiconductor wafers using conventional processes to form reduced-size memory devices due to the sequential processing technique used during fabrication.
FIG. 3 is a flow diagram illustrating a conventional process for etching a semiconductor wafer to form the memory gate stack 10 of FIG. 2. The method begins in step 40, where the multi-layer semiconductor wafer including the polysilicon layer 16, the ONO layer 24, the polysilicon layer 26, the silicide layer 28, and an oxide cap layer 30 overlying the silicide layer is covered with a photoresist layer. The photoresist layer is patterned in step 42 to form a mask to form the memory gate in step 42. The semiconductor wafer is then inserted into an oxide etch chamber in step 44, and an oxide etching operation is performed on the regions of the silicon oxynitride layer exposed by the mask. The semiconductor wafer is then moved in step 46 from the oxide etch chamber to a polysilicon etch chamber, where polysilicon etch processing is performed on the suicide layer 28 and the polysilicon layer 26. The semiconductor wafer is then removed from the polysilicon etch chamber and cleaned in step 48 to remove any remaining resist, and polymers remaining during the etching process. For example, the resist and sidewalls of the etched semiconductor may be cleaned using a hydrofluoric acid dip, plus a dry plasma (O.sub.2) clean, followed by a sulfuric acid bath. Following cleaning, another mask is formed in step 50 to cover areas that are not part of a memory core. The masked wafer is then moved to an oxide etch chamber in step 52 for etching of the ONO layer 24. Once the ONO layer 24 is etched, the semiconductor wafer is once again moved in step 54 to a polysilicon etch chamber in step 54 for etching of the polysilicon layer 16, followed by cleaning of the mask in step 56.
Hence, the conventional technique for forming the memory gate requires a substantial amount of etching in different etching chambers. Such processes require a substantial amount of handling of the semiconductor wafers, risking contamination of the wafer during transfers between etching chambers. In addition, the control of process parameters is reduced due to the movement of the semiconductor wafer between chambers during etching.